1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more specifically, to a semiconductor memory apparatus for improving area efficiency and a method of testing the same.
2. Related Art
Generally, in order to manufacture a semiconductor memory apparatus, a testing step is required to be performed because simulation results used for design and operation of chips used for an actual product may differ from each other. In order to actually reduce the defect rate of the semiconductor memory apparatus, various kinds of tests have been performed. Each test is performed by coding test codes of a plurality of bits that are input when a mode register set circuit defines a test mode. To this end, the semiconductor memory apparatus includes a decoder, which decodes the test codes of the plurality of bits to execute preset test modes.
The semiconductor memory apparatus according to the related art should include a plurality of signal transmission lines that transmit the test codes of the plurality of bits to the decoder in order to execute the test mode. However, the signal transmission lines should be long in length to be connected when considering the structure of a general semiconductor memory apparatus and thus, it is difficult to secure the stability of power supply of each signal line. In addition, as the integration of the semiconductor memory apparatus is gradually increased, it becomes difficult to secure enough space to arrange the signal lines. As such, the transmission lines for a large number of test codes provided for executing the test reduce the integration of the semiconductor memory apparatus, such that the high integration of the semiconductor memory apparatus reaches its limit.